If you are not quite sure what device the picture above represents - then perhaps you'll find these exercises useful and hopefully even entertaining!
For long time I wished to extend our "general programming" problems with exercises from the field of "programmable logic". Thus here comes a set of problems under tag VERILOG.
You may know that most of modern software is executed by less or more conventional microprocessors where instructions
are executed sequentially. Programmable Logic Devices (PLD) represent somewhat different approach, where engineer builds a kind of
logic scheme in which many singals may be processed by many blocks (logic gates) simultaneously. This approach has many applications -
from fast processing of some specific data - to building highly customized microprocessors.
Now, how such things are programmed? Quite a number of dedicated languages exists under the name of
Hardware Description Languages, but currently two of them
enjoy higher popularity, one is called Verilog HDL, another VHDL (yes, it is a bit confusing that the first seemingly would
abbreviate to the second). We'll go on with Verilog, though it doesn't mean VHDL is worse. They are somewhat different and
we need to pick some. Verilog is said to be bit more similar to general programming languages, like C and Algol-derived.
Also you'll see a bit more projects in Verilog on GitHub compared to VHDL (but just marginally).
To clarify: nowadays a somewhat extended version named SystemVerilog is popular - and so it's what we are going to use,
even though calling it simply "Verilog" for convenience.
Language is still more complicated at start, compared to Python or something we get used to. Thus we'll rely on 3-rd party materials for study. Here is something to begin with:
- Verilog Tutorial at asic-world.com - author proposes to try teaching basics of the language in one day
- EDA Playground - you can experiment with your code here, though simple registration is required
- SystemVerilog Homeworks @ GitHub - collection of exercises from "Digital Design School" - source files of exercises are in English (though some other files not) and provide very smooth learning curve - we'll reuse some of them.
- HDLBits - Verilog Practice - another set (large!) of small programming exercises in Verilog, quite gentle learning curve
Our website will also allow you to run your code (with the same runner which is used to check your solution). If you simply
hit the "Run" button, you'll at least will be able to check whether code compiles. You may add testbench module to code with
some initial block with $display statements and then you'll see some execution results. However you shouldn't submit modules with
such test-code, for most probably it will won't work properly in conjunction with testing code on the server.
Icarus Verilog v12 is a compiler used both by EDA Playground mentioned above and our website - you don't need to, but you may find it in prebuilt form for Windows and Linux if you want to play with it on your own machine. It is said to be lacking some of SystemVerilog's extended features so we may eventually move to something different - but for now it looks quite handy.
Credits
As mentioned, I wanted to add such exercises for quite a time already (you may remember we had a couple of logic-related problems) but as I don't have expertise in the field myself, it was predictably difficult. Recently inspiration came when I have got employed at the local company Yadro, which creates telecom solutions and has departments dedicated to electronics design and microprocessor design. I'm not even close to these departments but I was able to get basic hints from colleagues about choice of language and tools. Also the company runs the event Digital Design School which includes the large heap of Verilog homework problems mentioned above. So our warmest thanks to:
- Yuri Panchul - the said repository owner and a kind of Evangelist in this field - feel free to subscribe to Yuri's linkedin page and/or check Verilog Meetup
- Valentin Bulavskiy, Vitaliy Gumalevskiy and Aleksandr Kirichenko who provided initial guidance and hints about tools, language choice - and also directed me towards Yuri
- Michail Kuskov, Maxim Kudinov, Michail Trofimov, Kiran Jayarama, Petr Dynin, Maxim Vereshchagin, Alexey Fedorov and other people who contributed to the said repository of "homeworks"