RS flip-flop - CodeAbbey

RS flip-flop animation from wikipedia

This problem belongs to Verilog-related exercises, see foreword and useful links please.

Hopefully you have already tried building simple "combinational logic" in a Implication in Logic exercise. We are ready to make the next step and learn about probably the simplest piece of a "sequential logic", i.e such where output depends not only on the input, but also on the internal state (in other words - logic schematics with memory).

Flip-flops (sometimes known also as "triggers") are small elements which can indefinitely be in one of exactly two states. Thus they have single output, usually denoted as Q, which can be in true or false state. Inputs may toggle the state of the output (hence the name "flip-flop"), but some combination of input signals is valid for both states (i.e. it is a "hold" combination, meaning "just keep what state you have"). As it has exactly 2 states, it is actually 1-bit memory cell.

RS flip-flop has two inputs, Reset and Set. Depending on implementation they may work in slightly varying manner, but for simplisity let's consider the following version:

when both R and S inputs receive false (or 0, or low) signal, Q remains in whatever state it is
applying true to S turns Q to true (and this is preserved even when S returns to false, see above)
applying true to R resets Q to false (and this is also preserved when R returns to false)
it is "forbidden" to apply true to both inputs (not that flip-flop gets broken, but its state is not defined)

Animation above shows possible implementation of RS flip-flop based on two NOR elements (yes, two elements without memory brought together and coiled with feedbacks create element with memory) - red denotes true state while black is for false.

NOR is OR with inversion at the output (not-OR). It is possible to use NAND instead, but you'll see what we meant by implementation variations above. Also note the typical feature - flip-flop often may have additional Q' output (not-Q, Q-inverted) for convenience. It doesn't of course add more "state" to the cell, it is still just 1 bit.

The goal of this exercise is to create RS flip-flop schematic in Verilog. Use the following module and signal names to match checking code:

The goal of the exercise is to encode such function in Verilog language. Let the module be called implic with x and y as inputs and output called z. I.e. your code is likely to look that way:

module rsff (input set, input rst, output reg q, output reg qinv);

This reg keyword is something new here - without them outputs will be considered wire by default. You are advised to learn more about difference, but shortly speaking "reg" mean this signal may rely on internal state (unlike "wire").