Multiplexer switching between two signals of different frequency.
Try it live in falstad simulator here.
This problem belongs to set of Verilog-related exercises, see foreword and useful links please.
This element is not often met in the context of abstract, mathematical logic itself - but at the same time is extremely important building block
in real-life internal logic of digital electronic devices. For example - we have Intel 4004 CPU exercises here -
and if you look at wikipedia article about this processor, you'll see it has notably few pins - despite it seems to need at least 12 of them
to set address of memory and at least 4 more to feed or read data to that address. Explanation is that address and data "buses" (sets of pins)
are multiplexed.
From the viewpoint of "pure logic" the Multiplexer is a simple function with 3 inputs (call them X, Y and S) and one output (call it Z):
Z = (X & S) | (Y & ~S)
It is a bit tricky to grasp the idea from the formula, but it is very easy to explain in words:
Multiplexor makes output Z to reflect the state of either X or Y input depending on the state of S input.
I.e. it simply switches which of two inputs is fed to output (based on the third input). We can call X and Y the "data-inputs" and S
the "control-input".
While formula above doesn't now (hopefully!) seem very complex, the matter is complicated by the fact that multiplexer generally may need
to switch more than one single of inputs (e.g. 4 or 8 "channels") - and also actually the "width" of data lines (all inputs and output)
could be larger than 1-bit.
Returning to example of Intel-4004 chip above - it has only 4 pins actually to operate with 12-bit address and 4-bit data (16 bits
in total). Hence we conclude its multiplexer is 4-bit wide (e.g. there are 4 multiplexers in parallel on 4 parallel lines - but with
their control-inputs combined to work simultaneously). Also it should be able to switch between 4 channels (3 of them for 4-bit parts of
the 12 address lines and remaining 1 for 4 data lines). Also of course there exists "demultiplexer" to "untangle" combined data.
Of course writing such "wiring" in form of set of logic equations is going to be bulky (drawing them as schematic - even more). That's the reason why Hardware Description Languages (HDL) were invented.
Problem Statement
This exercise is to build multiplexer switching between 4 channels, each of them 4-bit wide. It is taken directly from the
Digital Design School homework by Yuri Panchul & Colleagues, as mentioned in the preface linked above. Look at this part of repository:
Combinational Logic @ SystemVerilog-Homework
You may notice that first 7 exercises out of 11 are about the same goal. They just suggest you may try different approaches to describing
the multiplexer:
- with "ternary" operator in "assign" statement
- with "if-else" in "always" block
- using "case"
- using array indexing
- using logic gates
- with 3 smaller 2-channel multiplexers
- with 2 smaller 2-bit wide multiplexers
As we use automatic checking of the result, we can't easily distinguish between all these variants of reaching the same goal, so anything will do - but we provide this exercise as convenient "testbench" for verifying your code if you decide to try these various approaches.
Please create your multiplexer as module conforming to this signature (the same as used in the "homework" for convenience):
module mux41 ( input [3:0] d0, d1, d2, d3, input [1:0] sel, output [3:0] y );
You see the brackets describing "width" of corresponding data lines. Four data inputs are d0, d1, d2, d3 and control input is sel.
P.S. you may also note the 4 remaining exercises in the folder mentioned above - they are curious puzzles of building well-known
simple logic functions using small multiplexer and constants. We make no provision for them at the moment, but they are funny and
you may want to try it on the paper or with EDA Playground.
P.P.S. if you remember our exercise on Logic Glitches, you'll suspect that the given "combinational" implementation of multiplexer may be not free of glitches - and that's correct, but glitch-elimination may happen elsewhere. For example, data are selected by multiplexer and set on data-lines with possible glitches, then read on receiving side (e.g. by memory module) is enabled by dedicated strobe (or "clock") signal, which is sent after all "transitional" effects are gone.