D flip-flop - CodeAbbey

D flip-flop is based on RS flip-flop with ANDs on inputs and edge-detector.
Try it live in falstad simulator here.

This problem belongs to set of Verilog-related exercises, see foreword and useful links please.

As we have learnt about RS flip-flop, we may feel it doesn't yet make proper "memory cell", because it needs signals on two different lines to rememer one of two states.

This issue is solved by D flip-flop, which has (at least) two inputs: D input is copied to output Q but only at the moment when C input goes from 0 to 1 (this is called "rising edge"). These letters stand for "data" and "clock".

If you may be curious how this is built from logic elements, see the image (or simulation) above. Here RS flip-flop is amended by some more components. What are those additions:

R should receive the same signal as S, just inverted (so here is upper NOT element)
both R and S signals, however, should be fed through a dedicated AND elements, so that they only "pass" to the flip-flop actually when these ANDs have their second inputs at "high"
these second inputs of ANDs are driven by "clock" signal (C input) which has edge detector (or glitch detector)

Often D flip-flop has additional inputs (and perhaps outputs). Popular 74..74 chip has additional R and S inputs and Qinv output. You may guess how they are added to the schematic above, as an exercise.

Problem Statement

Let's build D flip-flop with a single additional R input. Unlike D this input is not affected by C - i.e. applying signal there resets flip-flop immediately. This is very typical configuration as it allows resetting a group of flip-flops to "all zeroes" at once.

You probably will find it is much simpler in Verilog than in form of logic schematic. Use the following signature please:

module dff (input d, input clk, input rst, output q);

P.S. The same thing without edge-detector will "store" input signal simply on "high" level of the control-input - such form is called "latch" rather than "flip-flop" and its control-input is called "enable" (E) instead of "clock". It is less useful in "synchronous" devices like microprocessors - but is often used on its own for its straightforward functionality of storing signal (usually several lines in parallel with combined E input).