This problem belongs to set of Verilog-related exercises, see foreword and useful links please.
You should be acquainted with D flip-flop to proceed. Look at the picture above (and perhaps run simulation also). There are two such flip-flops chained, and each of them has negative feedback!
How it works?
Consider single stage - we link "inverting" output of the D flip-flop to its input. This will make it toggle on every positive edge
of the clock, because Qinv is always inversion of what D just have been, and hence it forces toggling again on every "clock cycle".
Another interesting effect is that if N positive edges will come to C input, this will result in N toggles on the output - but these
toggles are both positive and negative edges... So we have number of positive edges halved! With two stage we have them divided by 4
and chaining more D flip-flops we can get "division of frequency" by any value of form 2^K where K is number of stages.
Even more, if we regard outputs of flip-flops in reversed order, we see they actually show the count of positive edges in binary form! Though it seems we need to use negative outputs for the number to look correct (this actually depends on wiring and which edges clock flip-flops).
Such schematic is extremely important. Suppose that pulses are provided by some measuring sensor (e.g. radiometer) - with some more chips we can display number of pulses, say, per second - and this will be complete electronic measurement instrument!
But how would you make frequency divided by 10 for example? It is not a power of 2 but would be very useful, for example, to give decimal
representation of a number of pulses...
Problem Statement
Have a look at Halve Tokens exercise
in the "Digital Design School" repository. Here one is to build design which filters out a sequence of data and let only every second 1 to
the output.
Sequence is fed sequentially to the a input and clocked by clk input. E.g. our device should work very much like divider by 2, with
only small alteration. Here is an example of work (leftmost bits were generated first, clock signal is not showing, but it ticks for every bit):
input a: 1100111010001111
output b: 0100010010000101
However we think it is bit too simple (though you are advised to try solving it first). In this task please create design (in form of verilog code) which will filter out the sequence so that only every third bit shows up, e.g.:
input a: 1100111010001111
output b: 0000100010000010
Module signature should match the following:
module div3 (input clk, a, output b);